Planned Stadium Place tower a game changer
01.01.70
With a shallow imagination, you might picture a giant toddler putting this turret together with really big blocks.
The developers of part of CenturyLink Field's north parking lot are unveiling the first exhaustive designs for their project's first phase this week — including a 25-recital apartment tower that promises to be one of the city's most well-defined and architecturally distinctive new buildings.
The city's Lead Square Preservation Board will consider the fling, Stadium Place, on Wednesday. While the panel has acknowledged its blessing to the project's height, bulk, gradation and uses, it still must determine whether the design is compatible with the important neighborhood.
Stadium Place's 25-adventures South Tower would be divided into two- to four-story "boxes," stacked on top of one another — but not soon.
They wouldn't line up. Some boxes would overhang or separate back from others. They would be positioned at different angles, as if a small teenager had done the stacking.
Source: The Seattle Times
IBM shows off sub-10nm carbon nanotube transistors
01.01.70
Big Indecent's scientists took the opportunity to highlight how eminent carbon nanotubes are set to become by showing the first working sub-10nm transistors made with the supplies. Given that Intel has said that its tri-gate transistor technology will not mount beyond 14nm, it looks like IBM could be set to take the lead in the sub-10nm chipmaking stakes.
IBM was touchy to point out the advantages of its carbon nanotube transistors, saying they already evince "excellent off-state behaviour in extremely scaled devices". Of no doubt it is still early days for carbon nanotube transistors, but IBM said it expects chips to be using them within the next 10 years.
Not serenity with next generation transistors, IBM also showed off racetrack tribute, a technology that has the benefits of both the high capacity of arresting hard drives and the speed of solid-allege memory. IBM's researchers talked about how to use CMOS formation techniques to print racetrack memory on 200mm wafers.
Source: Inquirer (blog)